The present relates to an isolation technology for semiconductor devices.
A variety of methods and structures have been used to isolate areas on semiconductor devices. One widely used isolation technique is silicon trench isolation (STI), shown in FIG. 5. The field oxide 16 in the silicon substrate 2, is continuous with a surface oxide layer 10. FIGS. 1-4 illustrate the steps used to prepare the structure shown in FIG. 5. Thermal oxidizing forms an oxide layer 10 on the silicon substrate 2, followed by depositing a silicon nitride layer 6 using low pressure chemical vapor deposition (LPCVD), to form the structure shown in FIG. 1. Next, a photoresist layer 4 is applied, and patterned using a mask. Etching of those portions of the silicon nitride, surface oxide layer and silicon substrate not covered by the photoresist layer, in a single operation, opens a trench 8, as shown in FIG. 2.
Then, the photoresist layer 4 is stripped, and the substrate is cleaned. A thin oxide layer 14 is next grown by dry oxidation of the exposed portions of the silicon substrate. An oxide layer 12 is then deposited into the trench and across the surface of the structure by chemical vapor deposition (CVD), to form the structure shown in FIG. 3. Chemical-mechanical polishing (CMP) is used to planarize the surface, leaving the oxide layer 12 only in the trench, as illustrated in FIG. 4. Finally, the silicon nitride layer is removed, to form the field oxide 16, shown in FIG. 5.
During CMP, silicon oxide regions will be polished to a thickness that is about 200-300 xc3x85 thinner than adjacent silicon nitride regions, consistently. Across the surface of the wafer, however, the CMP is not uniform: center-to-edge non-uniformity may be as great as 500-1000 xc3x85 at the silicon nitride. This is also known as step height non-uniformity. This non-uniformity remains in the oxide isolation regions after the silicon nitride is removed, and may result in reduced device yields. It would therefore be desirable to have a method of forming isolation regions having an oxide thickness that is insensitive to non-uniformities caused by CMP.
In a first aspect, the present invention is a method of making a semiconductor structure, including removing a cover layer. The cover layer is on a first dielectric layer, the dielectric layer is in a trench in a substrate, and a protective layer is on the substrate.
In a second aspect, the present invention is a method of making a semiconductor structure, including filling a trench in a silicon substrate with a first oxide layer; forming a first nitride layer on the first oxide layer; and forming a second oxide layer on the first nitride layer. A second nitride layer is on the substrate, and the first oxide layer is also between the first and second nitride layers.
In a third aspect, the present invention is a silicon wafer, having isolation regions, the isolation regions including oxide having a thickness of 1000-7000 xc3x85 in trenches in the wafer. Differences in thicknesses between isolation regions on the edge of the wafer and isolation regions in the center of the wafer are less than 500 xc3x85.
In a fourth aspect, the present invention is a silicon wafer, having isolation regions, the isolation regions including oxide having a thickness of 1000-7000 xc3x85 in trenches in said wafer. At least 90% of the isolation regions have a thickness that varies at most 10% from the median isolation region thickness.
In a fifth aspect, the present invention is a method of making a semiconductor device from the above structures and/or wafers.
In a sixth aspect, the present invention is a method of making an electronic device from the above semiconductor device.